module Count(
  input        clock,
  input        reset,
  input        io_en,
  output       io_valid,
  output [7:0] io_out1,
  output [7:0] io_out2
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] a; // @[Counter.scala 62:40]
  wire  wrap_wrap = a == 8'he8; // @[Counter.scala 74:24]
  wire [7:0] _wrap_value_T_1 = a + 8'h1; // @[Counter.scala 78:24]
  reg [1:0] value; // @[Counter.scala 62:40]
  wire  wrap = value == 2'h2; // @[Counter.scala 74:24]
  wire [1:0] _value_T_1 = value + 2'h1; // @[Counter.scala 78:24]
  assign io_valid = io_en & wrap_wrap; // @[Counter.scala 120:{16,23}]
  assign io_out1 = a; // @[Count.scala 22:13]
  assign io_out2 = {{6'd0}, value}; // @[Count.scala 29:11]
  always @(posedge clock) begin
    if (reset) begin // @[Counter.scala 62:40]
      a <= 8'h0; // @[Counter.scala 62:40]
    end else if (io_en) begin // @[Counter.scala 120:16]
      if (wrap_wrap) begin // @[Counter.scala 88:20]
        a <= 8'h0; // @[Counter.scala 88:28]
      end else begin
        a <= _wrap_value_T_1; // @[Counter.scala 78:15]
      end
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 2'h0; // @[Counter.scala 62:40]
    end else if (io_en) begin // @[Count.scala 26:14]
      if (wrap) begin // @[Counter.scala 88:20]
        value <= 2'h0; // @[Counter.scala 88:28]
      end else begin
        value <= _value_T_1; // @[Counter.scala 78:15]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  value = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
